After completing the parasitic back- annotation flow, design is ready for generating GDSII. After that, you will run DRC, LVS checks on the layout, Extract parasitics and back-annotate them to the simulation environment. Then you will go ahead with completing the other layouts. You will learn the Layout Editor basics by concentrating on designing an “Inverter” through automatic layout generation. In the process, you will learn to use spectre, waveform window options, waveform calculator, etc. This circuit is verified by doing various simulations using spectre. Now you will create a new cell view called “Inverter_Test”, where you will instantiate “Inverter” symbol. Once inverter schematic is done, symbol for “Inverter” is generated. You will create a new cell called “Inverter” with schematic view and hence build the inverter schematic by instantiating various components. Attaching a technology library will ensure that you can do front to back design. You will start the lab by creating a library called “myDesignLib” and you will attach the library to a technology library called “gpdk180”. In the process you will create various components like inverter, differential amplifier, operational amplifier, R-2R based DAC and Mixed signal design of SAR based ADC, but we won’t be designing every cell, as the time will not be sufficient, instead we will be using some ready made cells in the process. You will finish the lab by running DRC, LVS and Parasitic Extraction on the various designs.
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Objective Objective of this lab is to learn the Virtuoso tool as well learn the flow of the Full Custom IC design cycle.
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